Taping out a design for fabrication is really a question of confidence on the quality of verification, knowing that more than 50% of all chips are born with functional issues. With the process geometries shrinking, gate densities increasing, verification could easily take more than 70% of the development cycle time. So, the extent to which you have verified and validated your design will determine if your chip will fall in or out of the 50% statistics.

In order to gain that extra confidence in taping-out a design, prototyping is fast becoming an industry wide practice. It is said, more than 40% of all ASICs (SoCs/ ASSPs) are either fully or partially prototyped in some form or the other.

Prototyping the design on FPGAs takes that confidence several notches higher. With advantages like fastest validation time, real-time validation, at-speed interfaces, real data handling, a real platform for early software development, post tape-out ECO validation etc. prototyping on FPGAs is fast becoming the preferred methodology.

Introducing the CAPP-XL54 CoreEL’s advanced FPGA based, generic, scaleable ASIC prototyping platform. With the CAPP-XL54, the idea is, to provide you with a platform to target your design and build upon it with additional interfaces, newer features, next generation enhancements and so on.

With four of the largest FPGAs, each CAPP-XL54 allows you to prototype up to 8 million ASIC gates. If you want more, the CAPP-XL54 can be scaled by stacking them. The CAPP-XL54 offers immense flexibility with plug-in daughter boards for all the interfaces you may want in your design.