The solution is targeted to video broadcast, video playout, video surveillance and DVR applications. With very low resource utilization, the decoder can be used for low-cost multi channel decode applications. The decoder solution is available for Xilinx Virtex-5, Virtex-4 and Spartan-3A DSP FPGAs.

Key features of the decoder solution are:

• Main profile level 4 decoder
• Supports resolutions from QCIF to HDTV 1080p
• Supports I, B and P slices
• Supports the YUV420 format
• Supports 8 bit color depth
• High decode throughput
• Decodes multiple video streams simultaneously
• Extracts sequence and picture parameter sets
• Supports multiple reference frames
• Manages reference lists
• Supports Exponential Golomb, CABAC and CAVLC decoding
• Supports Interlaced Coding (PicAFF, MBAFF)
• Performs 4x4 and 2x2 Inverse Hadamard Transform
• Performs Inverse Scaling and Transform for 4x4 and 16x16 blocks
• Intra prediction supports IPCM and all prediction modes for 16x16 and 4x4 blocks
• Inter prediction supports all partition sizes, 16x16 down to 4x4
• Inter prediction supports spatial B-Direct prediction
• Quarter-pel accurate Inter prediction
• Employs default weighted prediction
• Includes an In-Loop De-blocking Filter
• Error resilient design

Key benefits of the solution are:

• Optimized implementation resulting in lower cost per channel
• Higher density, more channels per FPGA resulting from the high
• processing rate of more than 400K macro blocks per second
• In-built scaling, for display from QCIF to HD 1080p resolution
• Full HD support, 1080p up to 60fps
• Ability to throttle frame rate from 24fps to 60fps
  

The IP Core is road mapped to support High Profile with 4:4:4 supporting 4:2:0, 4:2:2 and 4:4:4 chroma formats with 8 to 12 bit colour depth.