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  1a.

ASIC Design (Job Code: CGC/AD)

Location: Bangalore

Positions: Project Leads, Technical Leads, Sr. Design Engineers,
Sr. Software Engineers and Design Engineers

Qualification: M.E/M.Tech, B.E / B.Tech or equivalent in Electronics / Communication, Computer Science.

Experience: 2 to 10 years

   
 
Domains:
Multimedia (MPEG, Windows Media, DVB)
Telecom (SONET, ATM)
Networking (Ethernet, TCP/IP)
Storage Technologies ( iSCSI / SATA / Fiber Channel)
Processors (MIPS, ARM, PPC)
Interfaces (USB, PCIe, PCI-X) & Memories (DDR/DDR2, RLDRAM)
 
Required expertise:
SOC Architecture, Micro- architecture, RTL Design for ASICs.
ASIC Synthesis, STA, DFT, P&R, DRC, IC Layout Design, Physical Verification & Formal Verification
 
Skillsets:
Multimedia
Networking
Telecom
Storage
Interfaces
Processor
ASIC
Front end
VHDL
Verilog
RTL Architecture
Micro Architecture
Backend
Synthesis
STA
DRC
LVS
DFT
ATPG
Formal
Timing closure
 
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  1b. ASIC Front end Design (Job Code: CGC/AD)
   

Location: Bangalore

Positions: Project Manager

Qualification: M.E/M.Tech, B.E / B.Tech or equivalent in Electronics / Communication, Computer Science.

Experience: Experience: 10-12 years

   
 
Domains:
Networking (Ethernet, TCP/IP)
Processors (MIPS, ARM, PPC)
Interfaces (USB, PCIe, PCI-X) & Memories (DDR/DDR2, RLDRAM)
 
Required expertise:
Micro- architecture, RTL Design for ASICs.
Verification at module level
Should have at least executed at least 3 ASIC front end projects
 
Skillsets:
VHDL / Verilog
Micro Architecture definition
Scripting using Perl / tcl
Top level RTL integration
 
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