Proficient in VHDL/Verilog RTL Coding, System C/System Verilog.
Knowledge of C and Scripting using PERL, TCL/TK.
Proficient knowledge of FPGA’s and related devices and Timing Analysis.
Good in FPGA Synthesis & PAR Tools.
Proficient in Simulation tools like Modelsim, Questasim, and FPGA tools.
Proficient knowledge of different memory and interface devices.
Experience in Test Plan Definition, Coverage Driven Verification, Test Bench Development
& Functional Modelling.
Knowledge of MS Project.
Signal processing knowledge is desirable.
Ability to perform peer project reviews.
Soft Skills
Good presentation skills.
Excellent group work skills
Possess good interpersonal and Communication skills
Major Tasks and Responsibilities
Given an architecture, create work breakdown structure & understand effort estimations.
Get the designs implemented and/or executed.
Complete Project ownership from concept to delivery. This indicates identifying
risks, dependencies, creating mitigation plan, tracking project schedule and take
corrective action as required.
Create module levels details from architecture, coding, simulation and perform peer
review. Apply the methodologies for design, verification and validation.
Define, create and maintain all project related documentation.
Supervise and mentor at least 2 to 3 Design Engineers. Act as a PL in the absence
of supervisor.
Organize and manage conference calls, discuss with customers and resolve issues.
