| H.264 High Profile (HP) Decoder |
| |
| |
| Supported standard implementations |
 |
High Profile (4:2:0, 8-bit) @ Level 4.2 |
|
High 10 Profile (4:2:0, 10-bit) @ Level 4.2 |
|
High 4:2:2 Profile (4:2:2, 10-bit) @ Level 4.2 |
|
High 4:4:4 Profile (4:4:4. 12-bit) @ Level 4.2 |
|
H.264 Entropy only decoder @ Level 4.2 |
|
AVC Intra 50 (High 10 Intra) @ Level 3.2 and Level 4.1 |
|
AVC Intra 100 (High 422 Intra) @ Level 4.1 |
|
| |
| Input |
|
Transport Stream (TS) |
|
Video Elementary Stream (ES) |
|
| |
| Output |
|
Decoded stream in YUV 4:2:0/4:2:2/4:4:4 formats |
|
| |
| Salient Features |
|
Programmable color bit depth up to 12 bits |
|
Chroma format support: 4:2:0, 4:2:2 & 4:4:4 |
|
Supports resolutions from QCIF (176x144) to Full HD(1920x1080) progressive and interlaced |
|
Frame-rate up to 60 fps for HD decode |
|
Simultaneous multi-channel decode |
|
Single Channel 1080p60 / Dual Channel 1080p30 |
|
Fully validated on custom-built hardware using ITU-T and Fraunhofer test streams |
|
Optimized both for memory and performance |
|
Lower gate count |
|
Supports very low to very high bit-rates |
|
Supports both Intra frame only (H.264 Intra) and Inter frame (IPB) decoding |
|
Available on Xilinx & Altera FPGAs |
|
| |
| Deliverables |
|
Netlist / Verilog Source code of IP core |
|
Test bench |
|
Test report |
|
User manual |
|
Design document |
|
| |
| Target Applications |
|
Broadcast & Professional Video |
|
Broadcast Contribution & Distribution |
|
Video Servers |
|
Test & Measurements |
|
| |
| |
| For more information on the above IP Cores, please write to us at videoips@coreel.com |
